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HIP5020
Data Sheet January 1997 File Number
4243
Integrated-Power Buck Converter Controller with Synchronous Rectification
The HIP5020 is a high-efficiency, buck converter controller with synchronous rectification and integral power MOSFETs. Integrated current sensing eliminates the external resistor and saves power. The controller combines two methods of regulation: Current mode control for outstanding regulation response to large signal load transients, and Hysteretic mode control for high efficiency at low output currents. The HIP5020 controller offers a high degree of flexibility. Small components set the switching frequency, the soft-start interval and the load current boundary between Run and Hysteretic modes. These adjustments enable the designer to best optimize the trade-offs of cost, efficiency and size. The example application guide section illustrates these trade-offs with component and vendor suggestions for three circuit designs. These designs are suitable for use without modification. However, the block diagram, detailed description and HIP5020 component specifications enable further optimization to meet specific requirements.
Features
* High Efficiency - Above 95% * Integrated N-Channel Synchronous Rectifier and Upper MOSFETs - 75m Each * Wide Input Voltage and Load Range - 4.5VDC to 18VDC (5 to 12 NiCd Battery Cells) - Up to 3.5ADC * Automatically Switches Regulation Mode - Current Mode Control for Excellent Performance at High Load Currents - Hysteretic Control for High Efficiency at Light Load Currents * Flexible and Easy to Use - Ready-to-Use Example Applications - Custom Optimization with Small Components - Design and Simulation Software Available * Integrated, Low-Loss Current Sensing * Over-Current Protection * Adaptive Dead-Time - Eliminates Shoot-Through
Ordering Information
PART NUMBER HIP5020DB TEMP. RANGE (oC) 0 to 70 PACKAGE 28 Ld SOIC PKG. NO. M28.3
* 100kHz to 1MHz PWM Switching Frequency * Thermally Enhanced SOIC Package
Applications
* Notebook Computers * Portable Telecommunications * Portable Instruments
Pinout
HIP5020 (SOIC) TOP VIEW
VIN 1 VIN 2 VIN 3 PHASE 4 PHASE 5 6 PGND (WEB) 7 8 9 GND 10 FB 11 VINF 12 HMI 13 SLOPE 14 28 PHASE 27 PHASE 26 SD 25 SOFT 24 OVLD 23 22 21 20 19 CP18 CP+ 17 VCC 16 BOOT 15 CT PGND (WEB)
Typical Application
HIP5020 MODE CONTROL AND PROTECTION EFFICIENCY (%) 100 95 90 85 80 0.001 VIN = 6V VO = 5V VIN = 5V VO = 3.3V
VIN
INTERNAL SUPPLY
L1 14H
0.01 0.1 1 LOAD CURRENT (A)
10
C1 440F REGULATION AND CONTROL
VOUT
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
HIP5020 Functional Block Diagram
VCC VIN
CP+ CPCHARGE PUMP REGULATOR BOOT
CT
S OSCILLATOR
PWM LATCH R
PWM
UPPER GATE DRIVE
SLOPE
SLOPE GENERATOR PWM + CURRENT SENSOR
SD RUN
MODE CONTROL LOGIC SOFTSTART OVER-CURRENT PROTECTION
-
+ PHASE + -
PHASE
SOFT VINF
REFERENCE + 1.26V -
ERROR + AMP +
LOWER GATE DRIVE AND LOGIC PGND VCC 20A GND
+ HYSTERETIC
-
12pF
FB
HMI
OVLD
Pin Description
PIN NO 1, 2, 3 4, 5, 27, 28 6, 7, 8, 9, 20, 21, 22, 23 10 11 12 13 14 15 16 17 18 19 24 25 26 DESIGNATOR VIN PHASE PGND GND FB VINF HMI SLOPE CT BOOT VCC CP+ CPOVLD SOFT SD FUNCTION Input Voltage Switch Node Power Ground Signal Ground Voltage Sense Filtered Input Hysteretic Current Ramp Set Frequency Set Bootstrap Bias Bias Voltage Charge Pump Capacitor Over-Load Soft Start Shutdown DESCRIPTION Connection to the power source (Battery). Operates from 4.5VDC to 18VDC. Connect to output Inductor. Power Return and thermal interface. Solder these pins to a large copper ground plane. Connect to the output load return. A divider network scales the output voltage to 1.26VDC. Connect a low-pass (R-C) filter from VIN. A resistor to the HMI pin sets the peak inductor current level during hysteretic mode. A capacitor to ground sets the compensation ramp for current mode control. A capacitor to ground sets the oscillator frequency. A capacitor to Phase pin stores energy for the upper MOSFET drive. Output of charge pump regulator. Use bypass capacitor to ground. Connect a capacitor between these pins for the charge pump to generate bias power. The internal charge pump inverter is synchronized to the oscillator. A high level on this pin signals activation of the current limit protection. A capacitor to ground sets the soft start interval. A low level suspends operation for a low-dissipation shutdown mode.
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HIP5020
Absolute Maximum Ratings
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +20.0V Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +20.0V Shutdown Voltage . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VCC +0.3V Voltage on PGND. . . . . . . . . . . . . . . . . . . . . . -2V to +2V (Transient) All voltages are relative to GND, unless otherwise specified.
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) Plastic SOIC Package . . . . . . . . . . . . . . . . . . . . . . . 51 Plastic SOIC Package (with 1in2 copper). . . . . . . . . 42 Plastic SOIC Package (with 3in2 copper). . . . . . . . . 39 Maximum Junction Temperature (Plastic Package) . . . . . . . .125oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only)
Operating Conditions
Voltage Range, VIN . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +18.0V Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC Oscillator Frequency Range. . . . . . . . . . . . . . . . . . 100kHz to 1MHz
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
VIN = 6.3VDC, Components referenced from Figure 1. TYP values at TJ = 25oC and MIN, MAX limits are for TJ from 0oC to 125oC; Unless Otherwise Specified TJ = 25oC 0oC < TJ < 125oC MIN MAX UNITS
PARAMETER REFERENCE Reference Voltage Temperature Stability Hysteresis Width MODE CONTROL LOGIC Under-Voltage Lockout Threshold Under-Voltage Lockout Hysteresis Shutdown Threshold HMI Current Source POWER MOSFETs Drain Leakage Current On State Resistance Phase Rise and Fall Time CHARGE PUMP REGULATOR VCC Regulation Charge Pump Disable VCC Current - Run Mode VINF Current - Hysteretic Mode VCC Current - Shutdown
SYMBOL
TEST CONDITIONS
TYP
VFB
Total Variation, IO > IHMI
1.26 -
1.235 10
1.285 0.2 30
V mV mV
2
Hysteresis Mode; IO < IHMI
20
VCCUV VCCUV VSD IHMI
7.6 0.3 1.2 20
7.2 0.9 16
7.9 1.5 29
V V V A
IDSS rDS(ON) tr , tf
VDSS = 20V, VPHASE = 0 VBOOT - VPHASE = 12.6V; IPHASE = 2A IO = 2ADC
0.35 75 10
60 -
10 125 -
A m ns
VCC VINCPN ICC ICC - Idle ICC
VIN = 8.65V; FS = 100kHz; C4 = C5 = 1.0F
14.8 9.8
14.0 -
16.0 110 17
V V mA A A
FS = 100kHz VFB = 5V, VCT = 0 VSD = GND, VIN = 12V
4 78 2
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HIP5020
Electrical Specifications
VIN = 6.3VDC, Components referenced from Figure 1. TYP values at TJ = 25oC and MIN, MAX limits are for TJ from 0oC to 125oC; Unless Otherwise Specified (Continued) TJ = 25oC PARAMETER ERROR AMPLIFIER Internal Integration Capacitor Open-Loop Voltage Gain Gain-Bandwidth Product Input Bias Current SOFT START Current Source OSCILLATOR CT Charging Current Initial Frequency Accuracy Total Frequency Variation PROTECTIVE FUNCTION Current Limit Threshold PWM MODULATOR Modulator Gain Minimum On Time Minimum Off Time HYSTERETIC COMPARATOR Propagation Delay SLOPE GENERATOR Slope Capacitor Charge Current ISLOPE 80 A Step VFB 3 s 1.7 100 115 A/V ns ns IO PK 4.5 4 A VIN = 4.5 to 18V 126 3 7 110 140 10 A % % ISOFT 10 6 14 A AV GBW IFB VFB = 1.26VDC 12 89 7.2 3 -70 70 pF dB MHz nA SYMBOL TEST CONDITIONS TYP 0oC < TJ < 125oC MIN MAX UNITS
Example Application Guide
The HIP5020 provides the flexibility to meet differing needs. This section illustrates the trade-off of component selection for three DC-DC converter circuit designs. Each circuit is optimized for a specific goal: Circuit 1 is optimized for high efficiency, Circuit 2 is optimized for small size, and Circuit 3 is optimized for low cost. Figure 1 shows the schematic common to all three converter designs. Table 1 shows the expected performance parameters for each circuit. Table 2 gives the value of each component referenced in Figure 1. Table 3 provides a listing of suggested vendors for the major (or critical) components. Figures 2, 3 and 4 show the efficiency and transient performance of each circuit.
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HIP5020
VIN VCC D1 + VIN BOOT R5 C2 C12 C5 PHASE CPVINF C10 ON/OFF PGND SD FB CT SLOPE C6 C7 C8 R4 SOFT GND OVLD HMI R2 C9 R1 D2 R6 C1 CP+ HIP5020 C3 L1 VO C4
FIGURE 1. EXAMPLE APPLICATION CIRCUIT
TABLE 1. EXAMPLE APPLICATION PERFORMANCE PARAMETERS These characteristics are for the circuit shown in Figure 1 with the components given in Tables 2 and 3. PARAMETER Input Voltage - Typical - Range Switching Frequency Output Voltage Variation Line Regulation Load Regulation Output Voltage Ripple - Full Load - Light Load Efficiency - Full load - Peak - Light Load Estimated Circuit Area Tallest Component Normalized Circuit Cost Ratio of total circuit cost to Circuit 2 Initial Setting Input Voltage Range; IO = 1ADC IO = 0.1 to 3ADC, VIN = Typical Bandwidth < 20MHz IO = 3ADC, VIN = Typical IO = 50mADC, VIN = Typical IO = 3ADC, VIN = Typical 0.5 < IO < 2ADC, VIN = Typical IO = 50mADC, VIN = Typical CONDITIONS CIRCUIT 1 HIGH EFFICIENCY 3 Li-Ion Cells: 11.1 8.1 to 16 200 15% 3.3 3.5% 0.1 0.3 18 50 86 92 88 3.5 0.45 1.1 CIRCUIT 2 SMALL SIZE 2 Li-Ion Cells: 7.4 5.4 to 12 625 15% 3.3 2.2% 0.1 0.3 30 80 86 89 84 2.1 0.24 1 CIRCUIT 3 LOW COST 9 Nicd Cells: 10.8 8.1 to 16 120 20% 3.3 3.5% 0.1 0.4 20 70 86 90 72 3.6 0.68 0.75 UNITS VDC kHz V % % mV
% % % in2 in
TABLE 2. COMPONENT SUGGESTIONS FOR EXAMPLE APPLICATION CIRCUITS COMPONENT D1 D2 L1 C1 C2 C3 CIRCUIT 1 MBR0540 MBR0540 16H, RDC < 15m 2x - 220F, 10V OS-CON ESRMAX (100kHz) < 35m 100F, 20V OS-CON ESRMAX (100kHz) < 30m 0.1F 20% - Ceramic CIRCUIT 2 MBR0540 Not Used 5H, RDC < 22m 3x - 220F, 10V Tantalum ESRMAX (100kHz) < 100m 2x - 100F, 16V Tantalum ESRMAX (100kHz) < 100m 0.1F 10% - Ceramic CIRCUIT 3 1N4148 Not Used 26H, RDC < 25m 3x - 390F, 25V, Aluminum ESRMAX (100kHz) < 65m 2x - 390F, 25V Aluminum ESRMAX (100kHz) < 65m 0.1F 20% - Ceramic
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HIP5020
TABLE 2. COMPONENT SUGGESTIONS FOR EXAMPLE APPLICATION CIRCUITS (Continued) COMPONENT C4 C5 C6 C7 C8 C9 C10 C12 R1 R2 R4 R5 R6 CIRCUIT 1 1F 20% - Ceramic 1F 20% - Ceramic 470pF 5% - Ceramic 680pF 5% - Ceramic 0.1F 20% - Ceramic 220pF 5% - Ceramic 0.1F 20% - Ceramic 0.1F 20% - Ceramic 562K 1% 348K 1% 33.2K 200K 49.9K CIRCUIT 2 0.22F 10% - Ceramic 0.22F 10% - Ceramic 150pF 5% - Ceramic 390pF 5% - Ceramic 0.033F 10% - Ceramic Not Used 0.1F 20% - Ceramic 0.1F 20% - Ceramic 20K (Note) 12.4K (Note) 37.4K 2K Not Used CIRCUIT 3 1F 20% - Ceramic 1F 20% - Ceramic 820pF 10% - Ceramic 1200pF 5% - Ceramic 0.01F 10% - Ceramic Not Used 0.1F 20% - Ceramic 0.1F 20% - Ceramic 100K 1% 61.9K 1% 49.9K 2K Not Used
NOTE: Both resistors available in one SOT-23 from California Micro Devices part # PAC27A01 TABLE 3. SUGGESTED SUPPLIERS COMPONENT Capacitors Aluminum and Os Con Capacitors Aluminum and Ceramic Capacitors Tantalum and Os Con Capacitors Ceramic and Tantalum Capacitors Aluminum SUPPLIER Sanyo Panasonic Sprague AVX United Chemi-Con PHONE NUMBER 501-633-5030 0774-32-1111 207-324-4140 207-282-5111 708-696-2000 COMPONENT Inductors OCTA-PAC Inductors Inductors Magnetic Cores Powdered Iron Magnetic Cores Kool Mu Magnetic Cores Microlite SUPPLIER Coiltronics Pulse Engineering GB International Micrometals Magnetics AlliedSignal Inc. PHONE NUMBER 407-241-7876 619-674-8100 607-785-1109 714-630-7420 412-282-8282 201-581-7653
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HIP5020 Typical Performance Curves
100 VO = 3.3VDC OUTPUT VOLTAGE (V) VIN = 12.6V INDUCTOR CURRENT (A) 0.01 0.1 LOAD CURRENT (A) 1 10 95 EFFICIENCY (%) 90 85 80 75 70 0.001 VIN = 8.1V 3.46 3.34 3.32 3.30 3.28 1.5 1.0 0.5 0 0 40 80 120 TIME (ms) 160 200
FIGURE 2A.
FIGURE 2B.
FIGURE 2. HIGH-EFFICIENCY CIRCUIT 1 MEASURED PERFORMANCE EFFICIENCY vs LOAD CURRENT AND HYSTERETIC MODE OPERATION (VIN = 11.1VDC, LO = 0.1ADC
100 VO = 3.3VDC 95 EFFICIENCY (%) 90 85 80 75 70 0.001 VIN = 5.4V OUTPUT VOLTAGE (V) VIN = 12V INDUCTOR CURRENT (A) 0.01 0.1 LOAD CURRENT (A) 1 10 3.32 3.31 3.30 3.29 3.28 3.27 4 3 2 1 0 0.000 0.040 0.080 0.120 TIME (ms) 0.160 0.200
FIGURE 3A.
FIGURE 3B.
FIGURE 3. SMALL-SIZE CIRCUIT 2 MEASURED PERFORMANCE EFFICIENCY vs LOAD CURRENT AND 50% TO FULL LOAD TRANSIENT (1A/s)
100 95 EFFICIENCY (%) 90 85 80 75 70 0.001 OUTPUT VOLTAGE (V) INDUCTOR CURRENT (A) VIN = 14.4V 3.34 3.32 3.30 3.28 3.26 3 2 1 0 0 0.1 0.2 0.3 TIME (ms) 0.4 0.5
VIN = 8.1V
0.01
0.1 LOAD CURRENT (A)
1
10
FIGURE 4A.
FIGURE 4B.
FIGURE 4. LOW-COST CIRCUIT 3 PERFORMANCE PREDICTIONS EFFICIENCY vs LOAD CURRENT AND 50% TO FULL LOAD TRANSIENT (100A/ms)
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HIP5020
Design Information
The HIP5020 is optimized for battery power systems with a 4.5V to 18V input. The integrated MOSFETs along with an LC output filter form a synchronous rectified, step-down (buck) converter. The output is regulated at high output current by peak-current-mode PWM control. At light loads, the control automatically transitions to hysteretic mode to regulate the output. lower gate drive to turn-off the lower MOSFET when the inductor current reaches zero by monitoring the phase voltage (rDS(ON) * I). The HIP5020 regulates the output voltage with peak-current PWM control in Run mode. The peak-current-mode feedback, the MOSFETs and output inductor, L1 are all parts of the peak-current control loop. An outer voltage regulation loop then programs the peak current to the level required. When averaged over many switching cycles, the entire peakcurrent control loop can be simplified and described as a voltage controlled current source. Figure 5 shows a simplified diagram of this operation. The current source supplies the output capacitor and load. The outer voltage regulation loop consists of an error amplifier and compensation components. The error amplifier programs the inductor current (as described above) to the value required to regulate the output voltage. Both the error amplifier and hysteretic comparator monitor the feedback (FB) pin. During the Run mode, the feedback node voltage (VFB) is held to the reference voltage (REF) by the voltage feedback loop. VFB is related to Vo, R1 and R2.
CURRENT LIMIT HYSTERETIC COMPARATOR RUN REF+ REF ERROR AMP + +
Detailed Operating Description
The following description refers to symbols and components in the Functional Block Diagram and Figure 1. Figure 1 shows the HIP5020 in a DC/DC converter.
Operating Modes
The HIP5020 has 4 modes of operation; Shutdown, Start-up, Run and Hysteretic modes. The controller draws only 2A from the input supply in the Shutdown mode. This mode is activated when the SD pin is high. The controller enters the Start-up mode by releasing the SD pin, and the charge pump turns-on to increase VCC above the under-voltage lockout threshold. In the Start-up mode, the voltage on the SOFT pin increases at a rate set by the capacitor on the SOFT pin. The SOFT voltage limits the rate-of-rise of output voltage. The output voltage is regulated with peak current control in the Run mode at high output current. For low output currents, the controller automatically transitions to Hysteretic mode for output regulation. In this mode, the hysteretic comparator cycles the control on (RUN = High) and off (RUN = Low) as a function of the output voltage level. When off (RUN = Low), bias power is removed from most of the control's functions (only the reference and hysteretic comparator operate with RUN = Low). The converter replenishes the output capacitor charge with short duration power cycles (RUN = High) and the converter dissipates very little average power. A resistor (R4) programs the load current boundary (HMI) between the Run and Hysteretic modes.
PEAK-CURRENT CONTROL LOOP LOAD OUTPUT CAPACITOR
VO
REF-
HIP5020
FB R2
LOWER HMI LIMIT
R1
Run Mode
The HIP5020 operates in Run mode at high output currents. Each clock cycle of the oscillator sets the PWM Latch and turns-on the high side MOSFET (See the Functional Block Diagram). The current sensor supplies a voltage proportional to the current in the high side MOSFET. The PWM Comparator resets the PWM latch once the current signal exceeds the summation of the error amplifier and slope signals. The upper MOSFET turns off and the PWM latch enables the lower gate drive and logic. The current in the output inductor continues to flow, reducing the PHASE voltage (by displacing charge on the capacitances of the PHASE pin). The lower MOSFET turns-on after the voltage on the PHASE pin falls to ground as monitored by the phase comparator. The lower MOSFET remains `on' for continuous output inductor current until the next cycle. For discontinuous inductor current operation, the phase comparator signals the
FIGURE 5. SIMPLIFIED DIAGRAM OF OUTPUT VOLTAGE REGULATION AND MODE SWITCHING
Limiting the error amplifier output voltage range provides both current-limit protection and a mechanism for setting the load current boundary between the Run and Hysteretic modes. Figure 6 shows the modes of operation as a function of the error amplifier output and load current. The error amplifier output voltage tracks the inductor current. The upper error amplifier clamp limits the peak inductor current which reduces the pulse-width (or duty factor). This reduces the output voltage with a constant current characteristic. The lower error amplifier limit sets the minimum inductor current. For load current demand below the minimum inductor current, the excess current adds charge to the output capacitor and the output voltage increases. The voltage on the feedback (FB) pin also
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HIP5020
increases and the converter operates in Hysteretic mode. The lower error amplifier limit is the voltage on the HMI (Hysteretic Mode Current) pin. The HMI level (VHMI) sets the Run-to-Hysteretic mode load current boundary.
ERROR AMP OUTPUT
inductor current is regulated to a level proportional to VHMI. With very light loads, the converter replenishes the output capacitor charge in a few switching cycles (RUN = High) and the converter dissipates very little average power. Operation automatically transitions to Run mode as the load increases above the Run-to-Hysteretic mode load current boundary; the RUN signal simply stays High. The output voltage ripple during Hysteretic Mode is a function of the HMI (Hysteretic Mode Current) setting, output capacitor ESR, and the hysteretic voltage trip points. The approximate ripple voltage is:
V HMI * 1.7 * ESR + 2 * * ( R 1 R 2 + 1 )
HYSTERETIC MODE VHMI
RUN MODE
CURRENT LIMIT
OUTPUT LOAD
FIGURE 6. OPERATING MODES WITH THE ERROR AMPLIFIER CLAMPS
Where 2 is the hysteresis width (~20mV) and the 1.7 (A/V) factor is the error amplifier output voltage to peak current control gain (modulator gain).
Hysteretic Mode
The HIP5020 operates in the hysteretic mode with low output current. In this mode, the hysteretic comparator cycles the control on (RUN = High) and off (RUN = Low) as a function of the output voltage and the FB voltage level. Figure 7 illustrates the averaged Hysteretic Mode operation with reference to Figure 5. At light load, the error amplifier output voltage is held to the HMI voltage (VHMI). This level commands an inductor current that exceeds the load current. The excess current flows into the output capacitor which increases the output voltage (VO). The voltage feedback loop no longer holds VFB at the reference voltage. When VFB increases to the Upper Hysteretic Trip Level, the RUN signal transitions Low to power-down most of the control's functions, and the load is supplied by the output capacitor. After VFB (and the equivalent output voltage) drops below the Lower Hysteretic Trip Level, RUN transitions High, turning on the controller. The converter replenishes the charge on the output capacitor (C1). This cycle repeats to regulate the output voltage.
Protective Modes
The HIP5020 provides cycle-by-cycle current limiting and protects against over-current. The cycle-by-cycle current limit reduces the pulse width (duty factor) for peak inductor current levels exceeding the current limit (4A minimum). This results in a constant current output characteristic. The OVLD pin toggles high to indicate an overload condition. Should the current limit cause a small pulse width due to a saturating output inductor, over-current protection activates a soft-start cycle. The simultaneous occurrence of a minimum pulse width and a current limit signals an over-current condition. The converter enters the start-up mode by fully discharging the soft-start capacitor and inhibiting PWM operation. With a continuous overload, the over-current protection triggers the soft-start function which inhibits PWM operation until after the soft-start capacitor first fully charges to VCC and then fully discharges. This results in a very low average input current.
Soft-Start
The soft-start function is programmed by a capacitor on the SOFT pin (C10). This capacitor is initially discharged. Releasing the SD pin, or increasing VCC above the undervoltage lockout threshold initiates a soft-start interval. As the internal 10A source charges C10, the converter output follows the capacitor voltage, VSOFT. The control establishes closed loop regulation when the output voltage approaches the level set by R1, R2 and the reference. Initiating shutdown mode rapidly discharges capacitor C10. Releasing the SD pin initiates another start-up mode which charges up the capacitor C10 to VCC. Should the VFB exceed the upper hysteretic trip level, the internal 10A source stops charging C10. The soft-start interval will resume when VFB drops below the lower hysteretic trip level.
VO
2
VO REF
RUN
TIME
FIGURE 7. TYPICAL HYSTERETIC MODE OPERATION
The HIP5020 maintains peak-current control during Hysteretic mode. When the RUN signal transitions High, the control functions reenergize and the oscillator sets the PWM Latch which turns-on the high side MOSFET. The inductor current increases and resets the PWM latch to turn off the MOSFET. This cycle-by-cycle operation is identical to the Run mode operation. However, in hysteretic mode, the
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HIP5020 Detailed Component Selection
The application circuits shown in Figure 1 and described by Tables 1 and 2 illustrate component trade-off to achieve size, cost and efficiency goals. A design and simulation software program is available that simplifies the small signal component selection (http://www.semi.harris.com). This section provides additional guidance for selecting alternate components.
Switching Frequency
The oscillator produces a sawtooth wave on the CT pin with an amplitude of 1.26V. The switching frequency is set by C6. Select the closest standard capacitance value according to the following formula:
- 11 10 C6 = ----------- - 10 FS -4
Output Capacitor
The output capacitor, C1 smooths the output voltage ripple of the DC-DC converter. The size and value depend upon the output ripple requirement, the dielectric characteristics, the value of output inductance and the switching frequency. Choose a capacitor with a low impedance at the switching frequency to meet the output voltage ripple requirement. Use only specialized low-ESR capacitors intended for switching-regulator applications. Capacitor impedance above the switching frequency should also be minimized. During Hysteretic mode operation, the transition of RUN from low to high causes inductor current to ramp from zero to the HMI set level in a very short time. This rate of current change across the output capacitor's the equivalent series inductance (ESL) causes a voltage spike that appears (attenuated) on the FB pin. The ESL or the rate of current change must be limited to prevent the hysteretic comparator from toggling RUN between high and low. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor's impedance at the switching frequency (and the first few harmonics of the switching frequency) to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor.
Higher switching frequency decreases the size of output filter L1 and C1 and enables a higher bandwidth converter for faster response to a load transient. However, higher frequencies dissipate more power for a less efficient converter.
Control Loop Design
The HIP5020 realizes excellent transient response with proper control loop design. The device utilizes peak-current control with the entire current loop integrated within the HIP5020. Additionally, the HIP5020 includes a 12pF integration capacitor across the error amplifier. (See the Detailed Operating Description above.) Some applications need only add the resister R1 and capacitor C7 for a complete design. The capacitor, C7 adds a compensation slope to the peak current control loop (see Slope Compensation below). C7 shows up in the closed loop transfer function as peaking around half of the switching frequency. For a stable design, make sure the closed loop gain at half of the switching frequency is below -10dB. The error amplifier and compensation components regulate the output voltage by controlling the current loop (as shown in Figure 5). The compensation components shown in Figure 8 realize a lead-lag circuit. The resistor R1 adjusts the loop gain of the converter and resistor R6 and capacitor C9 set the pole and zero. The resistor R2 does not appear in the lead-lag transfer function. R2 sets the output voltage level. First stabilize control loop by selecting R1 and then determine R2 for the desired output voltage level.
VO R6
Output Inductor
The output inductor, L1 sets the ripple current and influences the converter efficiency. The ripple current, I is related to the inductance and switching frequency (FS), for continuous inductor current. Increasing the inductance or the switching frequency lowers the ripple current and the output ripple voltage. The inductance can be determined by:
V IN - V O V O L1 = --------------------- * --------I * F S V IN
REFERENCE 1.26V
ERROR TO AMP PWM + COMPARATOR -
C9 HIP5020 FB 12pF
R1
Inductance is a function of the core permeability, core size, and the square of number of turns. The power dissipation of the inductor is also dependent upon the number of turns and the core. In general, most of the power dissipation is in the inductor's winding. Therefore, use high permeability core material to minimize the number of turns. Be sure the flux at full load current does not saturate the core. Recommended core materials include: MicroliteTM from Allied Signal, ferrite, Kool-MuTM, molypermalloy (MMP), and powdered iron.
R2
FIGURE 8. LEAD-LAG COMPENSATION CIRCUIT
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HIP5020
Using the built-in 12pF integration capacitor across the error amplifier, the transfer function, G(s) for the lead-lag network is:
K 1 + s z G ( s ) = --- * ----------------------s 1 + s p 1 where K = ----------------------------------------- 12 R1 * 12 * 10 1 z = ---------------------------------------( R1 + R6 ) * C9 1 and p = --------------------R6 * C9
The output voltage regulation improves with the use of integrated resistor network. By integrating the resistors, the variations of R1 track the variations of R2. The ratio of R1 to R2 remains constant and this minimizes the output voltage variation to improve regulation. Integrated resistor networks are available in small SOT-23 packages such as the one used in Circuit 2.
Slope Compensation
Slope compensation is necessary to avoid current loop instability for duty ratios above 50%. Select C7 to set the amount of slope compensation according to the following:
L1 * 272 * 10 C7 MAX = ---------------------------------------VO
-6
The HIP5020 design and simulation software (available at the Harris WEB site) computes these values and greatly simplifies the following compensation design process. To design a DC-DC converter for stable operation: 1. Determine the output capacitor's ESR zero frequency, fESR which is given by: 1 ( 2 * * C1 * ESR ) 2. Place the compensation pole (p/2) at the ESR zero frequency, fESR . 3. Determine the desired converter bandwidth (or the frequency where the loop gain is unity). Bandwidth must be below 1/2 the switching frequency. A reasonable bandwidth is approximately 1/10 the switching frequency. 4. Select the compensation zero (z) well below the desired bandwidth frequency and adjust as necessary to achieve the desired phase margin (40o Minimum). 5. Adjust the gain (via R1) and iterate the compensation zero and gain as needed to achieve the desired bandwidth and phase margin. 6. Measure the closed-loop transfer function at both minimum and maximum input voltage and at both full load and the Run-to-Hysteretic mode load current boundary. Be sure to note the phase margin and the gain margin. The single component R1 can compensate the control loop if the detailed characteristics of the output capacitor, bandwidth, and switching frequency meet strict requirements. The bandwidth (or unity gain frequency) must be much greater than the ESR zero frequency (fESR) and much less than twice the switching frequency. Additionally the break frequency of output capacitor's ESL must be much greater than the switching frequency. If these conditions exist, the ESR zero provides the necessary phase boost. However, note that the ESR is not a well controlled parameter and is variable with temperature and aging. Select R1 for the proper compensation gain and confirm the selection with closed-loop measurements. Additionally determine the worst case ESR variation and estimate this effect on converter stability.
This value of capacitance provides a compensation ramp that is 1/2 of the reflected output inductor decreasing current slope.
Charge Pump and Bootstrap Design
The charge pump and bootstrap circuit supply the internal bias power for the HIP5020. The majority of the bias power goes to gate drives. The charge pump operates at the switching frequency for input voltage below 9.8V. Select capacitors C4 and C5 according to the following:
-6 0.088 C4, C5 MIN = -------------- + 0.12 * 10 FS
The gate of the upper N-Channel MOSFET is driven above the input voltage by the internal gate drive with power supplied by the bootstrap circuit D1 and C3. A fast recovery, low leakage diode is recommended for D1. C3 should be a high quality ceramic capacitor.
Hysteretic Mode Current Setting
The voltage on the HMI pin sets the load current boundary between Run mode and Hysteretic mode. This setting enables the designer to trade-off efficiency and output voltage ripple at low output current. The output voltage ripple is higher in Hysteretic mode as compared with Run mode. Many systems can tolerate higher power supply ripple at light loads because the reduced load induced ripple. The designer should select the load current boundary based upon converter efficiency characteristics and known load characteristics. For example, a HIP5020 converter powering a microprocessor load might select the HMI boundary between the sleep and active states of operation. The ripple voltage is highest for load current just below the mode boundary. The ripple voltage is a function of the hysteresis width, the resistors R1 and R2, the hysteretic current setting (HMI) and the output capacitor ESR as described in the Hysteretic Mode section. Figure 9 shows the efficiency versus load for two different VHMI settings. The efficiency at light load current is higher with a higher settings. The efficiency at light load current is higher VHMI setting. However, the more efficient design has
Output Voltage Setting
The resistor divider R1 and R2 sets the output voltage as a function of the reference voltage. Select R1 to achieve the desired bandwidth then determine R2 from:
1.26 R2 = R1 * ------------------------V O - 1.26
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HIP5020
a higher ripple voltage for load current between 0.2A and 0.6A. If the load is sensitive to power supply ripple during this load range, the lower efficiency HMI setting should be used.
100 95 90 85 80 VHMI = 0.15V 75 70 CIRCUIT 1: VIN = 6VDC TA = 25oC VHMI = 0.5V
R5 and C10 form a low-pass filter for the bias supply (VINF) of the reference and hysteretic comparator functions. A 2k resistor for R5 and a 0.1F Capacitor for C10 is recommended. Locate C10 directly across the VINF and GND pins.
Thermal Design
The power ground (PGND) pins of the SOIC package provide a thermal conduction path for removing heat from the HIP5020. Inside the package, the HIP5020 die is mounted on a copper structure with connections to PGND (pins 6, 7, 8, 9, 20, 21, 22, and 23). Solder the SOIC to a circuit board with a copper ground plane to remove heat from the package. With good component layout and 3 square inches of copper ground plane, the junction-toambient thermal resistance is 36oC/W. Most of the converter's power dissipation will be in the HIP5020 and the output inductor, L1. The power dissipated in the HIP5020 can be estimated from the converter's full load efficiency and subtracting the inductor's power dissipation ( I O 2 * R DC ). The junction temperature rise above ambient is this power multiplied by the thermal resistance. Use the HIP5020 design and simulation software for more accurate thermal simulations. Be sure to keep the junction temperature below 125oC for reliable operation. Careful component layout and good thermal design maximized the efficiency and reliability of the converter.
EFFICIENCY (%)
0.001
0.01
0.1 LOAD CURRENT (A)
1
10
FIGURE 9. EFFICIENCY vs LOAD CURRENT
The voltage on the HMI pin is used to clamp the lower limit of error amplifier output voltage and the minimum peak inductor current. This voltage is set by a 20A current source and the resistor, R4.
Soft-Start
Set the Soft-Start capacitor, C8 so that the output voltage ramps to its final value with a current between the hysteretic mode current and the rated current. The minimum value for C8 can be determined from:
10 C8 MIN = T SOFT * -------------V
-5
Detailed Characteristics
Charge Pump Regulator
The charge pump regulator supplies control power (VCC) to the internal functions of the HIP5020. The charge pump operates for input voltage levels below 9.8V and is disabled for input voltages above 9.8V. Figure 10 shows the charge pump output voltage (VCC) as a function of the input voltage (VIN). For input voltages below 9.8V nominally, the charge pump operates in two regions - as a voltage doubler and as a voltage regulator. The charge pump operates as a normal voltage doubler when VCC is below approximately 14.8V. The charge pump limits VCC to approximately 14.8V in the regulation region. For input voltages above 9.8V, the charge pump is disabled and VCC follows the input voltage less a diode drop.
REF
C1 * V O where T SOFT = --------------------3A
Larger values for C8 will extend the soft-start interval, TSOFT. Any loading during the Start-up mode lengthens TSOFT.
Bypass and Filter Capacitors
Capacitor C12 supplies the leading edge PWM current each switching cycle. A high quality (X7R dielectric ceramic) 0.1F surface-mount capacitor is recommended. Locate C12 directly across the VIN and PGND pins. Bypass the internal VCC supply with a high quality (X7R dielectric ceramic) surface-mount capacitor (C4). Locate C4 directly across the VCC and GND pins. The value for capacitor C5 should be selected as described in the Charge Pump Regulator above. A single high quality (X7R dielectric ceramic) capacitor is usually adequate. Some applications may need a high capacitance, electrolytic for charge-pump operation. For these applications, a high quality capacitor in parallel with the electrolytic is recommended. Locate C5 directly across the CP+ and CP- pins.
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HIP5020
20
REGULATION REGION 15 VCC (V) VOLTAGE DOUBLER REGION 10 CHARGE PUMP DISABLED 5
applications and external loads. Be sure that the load can tolerate the VCC voltage variation with input voltage. During Hysteretic Mode, the external load should be removed when the converter turns off. Note that the charge pump and oscillator are disabled with RUN low (see Operating Modes). The external load could cause an under-voltage lockout trip and subsequent soft-start cycle.
Light Load Power Dissipation
The converter efficiency and power dissipation at light load is mainly a function of the bias supplied to the HIP5020. Figure 12 shows the input current as a function of the input voltage for the two states of the RUN signal. IIN is summation of both the current into the VIN and VINF pins. The curve for IIN with the RUN signal High does not include the gate drive power. The gate drive power is a function of the MOSFETs gate charge, voltage and switching frequency. Figure 13 shows the combined gate energy required by the internal MOSFETs with the charge pump characteristics. To determine the total bias power: 1. Multiply the value in Figure 13 by the switching frequency. 2. Add the product of the voltage and current from the RUN = High curve in Figure 12.
VIN = 12VDC
0
5
10 INPUT VOLTAGE (V)
15
20
FIGURE 10. CHARGE PUMP REGULATOR INPUT VOLTAGE CHARACTERISTICS
14 CIRCUIT 3 VIN = 8.65VDC
VCC (V)
12
3. Multiply by the ratio of RUN time to the Hysteretic period. 4. Add the product of the voltage and current from the RUN = Low curve in Figure 12.
0.4
10
VIN = 5VDC
GATE ENERGY (J)
8 1 2 5 10 20 EXTERNAL LOAD (MADC) 50 100
0.3
FIGURE 11. BIAS VOLTAGE (VCC) vs EXTERNAL LOAD CURRENT
100 RUN = HIGH CT - GND
0.2
0.1
80
0.0
0
5
10 VIN (V)
15
20
IIN (A)
60
FIGURE 13. MOSFET GATE ENERGY CHARACTERISTICS vs INPUT VOLTAGE
40
MOSFET On-Resistance
Conduction losses are a significant portion of the power dissipation in a DC-DC converter. The HIP5020 conduction losses are the product of the square of the average output current and the MOSFET on-resistance - rDS(ON). The rDS(ON) of the MOSFETs is a function of VCC and junction temperature. VCC changes with the input voltage as shown in Figure 10 above. Figure 14 shows the maximum rDS(ON) of both MOSFETs as a function of input voltage for a junction temperature of 25oC. The junction temperature of the HIP5020 also effects rDS(ON). Figure 15 shows the rDS(ON) as a function of temperature for three gate voltage levels.
20 RUN = LOW 0 0 5 10 VIN (V) 15 20
FIGURE 12. BIAS POWER CHARACTERISTICS
The charge pump can be used to supply current for external loads on the VCC pin. Figure 11 shows the regulation characteristics of the charge pump in the various operating regions. These characteristics are for a DC-DC converter (Circuit 3) operating at 100kHz and with 1F capacitors for C4 and C5. The charge pump may not be suitable for some
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HIP5020
The rDS(ON) can be estimated at a given input voltage and junction temperature as follows: 1. Assume that the gate voltage is equal to VCC. Find the gate voltage at 25oC from Figure 10. 2. Multiply this number by the rDS(ON) shown in Figure 15. Interpolate as necessary.
Application Hints
Short Duration RUN Interval
Some converter designs may observe a series of short run interval pulses (RUN = High) in hysteretic mode that can reduce the light-load efficiency. The run interval is interrupted by the voltage on the FB pin crossing over the Upper Hysteretic Trip Level before the output capacitor gains sufficient charge. This operation can be caused by a number of factors: 1. Poor physical layout. Use wide traces to connect the power components. 2. Poor component choice. Use only power supply specific electrolytic capacitors. Additionally use ceramic capacitors in parallel with the bulk electrolytic capacitors. 3. Sudden voltage excursions across the output capacitor and the error amplifier output. Be sure to clear up any layout problems first. Poor layout not only causes efficiency problems, but can be a source of noise for surrounding circuits. If the short run interval is still observed, a capacitor can be added across each R2 and R4. During the transition of RUN from low to high, the voltage on the FB pin starts at the Lower Hysteretic Trip Level. The error amplifier activates and its output slews to VHMI. This causes an increase in VFB due to current in the compensation capacitor. Adding a capacitor across R4 slows the rate of HMI voltage increase during the transition of RUN from low to high and decreases error amplifier slew rate. Voltage excursions across the output capacitor and circuit board traces after the transition of RUN from low to high results in an increase in VFB . As the inductor current ramps to the HMI level, the output voltage increases due to the output capacitor's ESR and ESL. This voltage spike is attenuated by the resistor divider, R1 and R2 but still appears on the FB pin. A small capacitor across R2 further attenuates any output voltage spikes. The small capacitor eliminates the short duration RUN interval, but will not reduce the output voltage spikes. A better solution may be a better, higher quality output capacitor with low ESR and ESL.
0.10 TJ = 25oC 0.09
rDS(ON) ()
0.08
0.07
0.06
0.05
2
4
6
8
10 12 14 INPUT VOLTAGE
16
18
20
FIGURE 14. rDS(ON) vs INPUT VOLTAGE
140 130 120 110 rDS(ON) (m) 100 90 80 70 60 0 20 40 60 80 TEMPERATURE (oC) 100 120 VG-S = 18V VG-S = 8V VG-S = 12V
FIGURE 15. rDS(ON) vs JUNCTION TEMPERATURE
Bootstrap and Phase Diodes
The bootstrap function requires a diode D1 to supply gate drive power for the upper N-Channel MOSFET. A Schottky is recommended for most applications due to its fast switching speed and low forward voltage. A fast-recovery diode can be used in low switching frequency, cost sensitive applications. Many applications will not need a Schottky diode from phase to ground. The internal body diode of the integrated MOSFET is sufficiently fast. A small Schottky diode can be added to improve the light load efficiency. This diode only conducts during the short intervals (< 50ns) before and after the lower MOSFET conducts. In most cases, a Schottky rated for 0.5A is sufficient.
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HIP5020
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